1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating it, and more particularly to reduction of the number of mask steps in a process of fabricating a power MOSFET, and the like.
2. Description of the Related Art
Hereinafter, a power MOSFET of the prior art will be described with reference to the drawings. FIG. 19 is a section view showing the structure of a planar type power MOSFET of the prior art.
In the power MOSFET, as shown in FIG. 19, a drain layer 2 consisting of an n− epitaxial layer is formed on an n+ semiconductor substrate 1, and a channel layer 3 is formed in a part of the drain layer by diffusion of a p-type impurity. A body region layer 5 is formed at the center of the channel region by diffusing a p+ impurity. A source region layer 4 which is formed by diffusion of an n+ impurity is disposed in the surface layer of the channel layer 3 so as to surround the body region layer.
A gate insulating film 6 and a gate electrode 7 are sequentially formed on the channel layer 3 so as to overlap with a part of the channel layer 3 and the source region layer 4. A PSG (Phospho-Silicate Glass) film 8 is formed so as to cover the gate insulating film and the gate electrode. In the PSG film 8, an opening is formed in the region where the body region layer 5 is formed and a part of the region where the source region layer 4 is formed. The body region layer 5 and the part of the source region layer 4 are partly exposed. A wiring layer 9 for contact to the body region layer 5 and a part of the source region layer 4 is formed so as to cover the layers and the PSG film 8.
The steps of fabricating the power MOSFET will be described with reference to FIGS. 20 to 25.
First, the n− drain layer 2 is formed on the n+ semiconductor substrate 1 by epitaxial growth. Next, a thick oxide film is formed on the drain layer, and a photolithography process selectively forms a resist film. A patterning process is conducted on the thick oxide film with using the resist film as a mask, and then an oxide film, which will be formed as the gate insulating film is again formed. Although the thick oxide film is not shown in any of FIGS. 20 to 25, the thick oxide film is required in a region where a bonding pad is to be formed.
Thereafter, a polysilicon layer is formed on the entire surface of the semiconductor substrate, a photoresist film is formed, and then a patterning process is conducted by the photolithography method. The polysilicon layer and the oxide film are etched with using the patterned resist film as a mask, so that the gate insulating film 6 and the gate electrode 7 are formed as shown in FIG. 20.
Next, a p-type impurity is injected with using the gate insulating film 6 and the gate electrode 7 as a mask, to form the channel layer 3 on the drain layer 2 as shown in FIG. 21.
As shown in FIG. 22, a photoresist is then applied to the entire surface, and a patterning process is conducted by the photolithography method so that an opening is formed in a part of the channel layer 3. A p-type impurity is injected into the channel layer 3 with using the patterned resist film PR1 as a mask, to form the body region layer 5.
As shown in FIG. 23, the patterned resist film PR1 is then removed away, a photoresist is again applied to the entire surface, and then patterned by the photolithography method so that a resist film PR2 is formed on the region where the body region layer 5 is formed, and an n-type impurity is thereafter injected into the channel layer 3 with using the resist film PR2, the gate electrode 6, and the like as a mask.
Thereafter, the PSG film 8 is formed on the entire surface as shown in FIG. 24. A photoresist (not shown) is again applied and the resist is patterned by the photolithography method so that an opening is formed on the body region layer 5 and a part of the source region layer 4.
Next, the PSG film 8 is etched with using the resist as a mask to expose the regions of the body region layer 5 and a part of the source region layer 4 (FIG. 25).
A film of a metal such as aluminum is then formed on the entire surface by sputtering or vapor deposition. A resist film is formed, and then patterned by the photolithography method. The metal film is etched away with using the patterned resist film as a mask to form the wiring layer 9, thereby completing the power MOSFET having the structure shown in FIG. 19.
In the above, a planar type power MOSFET has been described. As a power MOSFET of another kind, known is a trench type power MOSFET in which a trench is formed in a substrate and a gate electrode is embedded in the trench.
Hereinafter, a trench type power MOSFET will be described with reference to FIG. 26.
As shown in FIG. 26, the power MOSFET comprises a semiconductor substrate 11, an n− drain layer 12 which is formed on the substrate by epitaxial growth, and a p-type channel layer 13.
In a part of the channel layer 13 and the drain layer 12, a trench which passes through the layers is formed. A gate insulating film 16 made of an oxide film or the like is formed on the inner face of the trench. A gate electrode 17 made of polysilicon or the like is formed so as to fill the trench.
A source region layer 15 of an n+ impurity is formed in the surface of the channel layer 13 so as to be on both the sides of the gate electrode 17. A p+ body region layer 14 is formed at a center portion of the source region layer 15.
A PSG film 18 is formed so as to cover the gate electrode 17. An opening is formed in a part of the PSG film 18. The body region layer 14, and a part of the source region layer 15 which surrounds the body region layer are exposed through the opening. A wiring layer 19 for contact to the body region layer 14 and the part of the source region layer 15, is formed on the layers and the PSG film 18.
For the above-described planar type power MOSFET, a photomask for a photolithography process for patterning is required in each of the following steps:
1) the step of forming the mask for forming the thick oxide film for the bonding pad,
2) the step of forming the patterning mask for forming the gate electrode (FIG. 20),
3) the step of forming the resist mask for forming the body region 5 (FIG. 22),
4) the step of forming the resist mask for forming the source region 4 (FIG. 23),
5) the step of forming the resist mask in the case where the contact hole of the source region 4 is formed in the PSG film 8 (FIG. 25), and
6) the step of forming the resist mask for patterning the wiring layer.
As a result, six photomasks are required in total.
Therefore, problems in that the number of mask steps and accompanying steps is very large, that the production process is complicated, and that the production cost is high are produced.
In the production process of a trench type power MOSFET, a body region layer and a source region layer are formed with using a photoresist as a mask. Therefore, the fine patterning is limited and it is difficult to increase the cell density.